C166 Manual Full Djvu

File Name:C166 Manual Full Djvu.pdf


ENTER SITE »»» DOWNLOAD PDF


CLICK HERE »»» BOOK READER


Size: 4611 KB
Type: PDF, ePub, eBook
Uploaded: 30 May 2019, 17:26
Rating: 4.6/5 from 552 votes.
tatus: AVAILABLE
Last checked: 3 Minutes ago!
eBook includes PDF, ePub and Kindle version
In order to read or download C166 Manual Full Djvu ebook, you need to create a FREE account.

✔ Register a free 1 month Trial Account.
✔ Download as many books as you like (Personal use)
✔ Cancel the membership at any time if not satisfied.
✔ Join Over 80000 Happy Readers

For the Star Trek 10 film, see Star Trek: Nemesis. For the ST10 postcode, see ST postcode area. It was first released in 1993 and is a controller for measurement and control tasks. It uses the well-established RISC architecture, but features some microcontroller-specific extensions such as bit-addressable memory and an interrupt system optimized for low-latency. When this architecture was introduced the main focus was to replace 8051 controllers (from Intel ).Retrieved 2019-06-18. You can help Wikipedia by expanding it. v t e By using this site, you agree to the Terms of Use and Privacy Policy. The following code is working. May someone kindly explain in details how C167 controller interpret it.The C166 compiler utilizes DPP addressing mechanism of the C167 microcontroller for near data pointers, which means that a near absolute address will most likely be translated to a different physical address. To specify absolute physical address, you have to use far, huge or xhuge pointers. Use macros from absacc.h, they were designed for that: This is written in Assembly code which was obtained from the web site, and not from the compiler. Somehow, the bit 15-14 had to be set to 10B. I am not able to get any information from the C167 manual. Maybe you can help. The DPPx-Registers should be set to fixed values in the startup sequence (start.a66) and the compiler usually assumes that they are not changed. The address offset (14 bit) is 1555h. By adding 4000h and 1555h you get the physical address 5555h. Also beware when using EXT-instructions in a Class B trap handler: save and reset the TFR-Register first.) Bits 15 and 14 of R12 (which was used as a pointer in your example) select which of the four DPPs to use. 10 binary means DPP2.In address 0x9555, the two MSBits are 10B or 0x02. This means that DPP2 is used. Since DPP2 contains the value 0x01 you have to replace the two MSBits of the address with 0x01. So 1001B becomes 0101B which results in the address 0x5555. http://www.zulassungsdienst4you.de/bilder/crosman-model-1077-manual.xml

c166 manual, c166 assembler manual, c166 instruction set manual, c166 user manual, c166 compiler manual, c166 manual.

DPP usage is kind of a pain in the butt when you are debugging but it does allow you locate data and such anywhere in the 16 Mbyte address space and still use 16-bit addressing mode. -Walt. Microcontrollers User’s Manual, V 2.0, Mar. 2 001 Instruction Set Manual for the C166 Family of Infineon 16-Bit Single-Chip Microcontrollers Attentio n please! The informat ion herein is given to descr ibe cer t ain componen ts and shall not be con sidered as w arrante d chara cte ris tics. T erm s of d elivery a nd r ights to technica l change reser ved. W e he reby disclaim any and all warranties, includin g but not limited to warranties of non-infri ngement, regarding circuits, descr iptions and c har ts state d herein. Infineon T echnologie s is an approved CECC m anuf acturer. Info rma tion F or fur th er inf or mation on technology, deliver y ter ms and cond itions and pr ices pleas e contact your nearest Infineon T ec hnologies Office in Ger many or our Infineon T echnologie s Representat ives worldwide. Warnings Due to technic al requirem ents compone nts may cont ain dangerou s substance s. For inf orm ation on the t ypes in question plea se contac t y our nea rest Infineon T echn ologies Of fice. Infineon T ech nologies Com ponents may only be used in life-suppor t devices or systems with the e xpress wr itten approval of Infineon T echnolog ies, if a f ailure of such componen ts can reason ably be expected to cause the failure of that lif e-suppo r t de vice or syst em, or to aff ect the sa f ety or eff ective ness of that d e vice or sys tem. If t hey f ail, it is r easonable to as sume that the he alth of the user or other pe rsons may be endanger ed. Instruction Set Manual for the C166 Family of Infineon 16-Bit Single-Chip Microcontrollers This allows to equip eac h specific applicatio n with the micro controller tha t fits best to the required fun ctionality and performance. http://clairvoyantinfotech.com/demo/images/crosman-mark-ii-target-pistol-manual.xml

Still the Infi neon fa mily concept p rovides an easy p ath to upgrad e existing ap plications or to climb the next level of performance in order to reali ze a subsequen t more sophistic ated design. This manual also desc ribes the di fferent addres sing mech anisms and the relation between the logical addre sses used in a program and the res ulting phys ical address es. There is also information p rovided t o calculate the executi on time for spe cific instru ctions depending on the used address loc ations and also spec ific excep tions to the standard rules.The tab le shows whic h addressing mo des may be use d with a speci fic inst ruction and als o the instruct ion lengt h depending o n the selecte d addressing mode. Both orderin g schemes (hex adecimal op code and mn emonic) ar e provided in more detailed li sts in the f ollowi ng section s of this m anual. Note: The ATOMIC and EXTended ins tructions are no t available in the SAB 8XC166(W) devi ces. They are m arked in th e cross-referen ce table. This en ables the user to identi fy the right instruc tion(s) for a specif ic required function.Th is helps to iden tify specific instructions when reading executabl e code, i.e. during th e debugging phase. Note: The ATOM IC and EXTende d instructi ons are not ava ilable in the SAB 8XC166(W) devices. 00xx.xxxx B: EXTS or ATOMIC 01xx.xxxx B: EXTP 10xx.xxxx B: EXTSR o r EXTR 11xx.xxxx B: EXTPR Conditional JMPR Instructions The conditi on code to be tested fo r the JMPR instru ctions is s pecified b y the opcode. Two mnemonic representati on alternativ es exist f or some of the condit ion cod es (conditio n codes are described in Table 5 ). BCLR and BSET Instructions The positi on of the bi t to be set o r to be c leared is s pecified by th e opcode. Note: The 8XC166(W) dev ices also do not recogni ze ATOMIC and EXTended in structions, but rather decode an undefined o pcode. https://labroclub.ru/blog/elna-3003-instruction-manual

The example furth er down on this page lists the ele ments of a de scription and demonstrate s how the inf ormation give n for each instruction is arranged. The next pages ex plain the eleme nts of an instructio n description (see example), and then all in structions a re listed ind ividually. The instruc tions are orde red alphabe tically. Z Effect of thi s instructio n on flag Z. V Effect of thi s instructio n on flag V. C Effect of thi s instructio n on flag C. N Effect of thi s instructio n on flag N. Note: For mo re informat ion about th is item ple ase refer to th e Assembler manu al. Oper ati on This part presen ts a logical description o f the operat ion performed by an in struction by means of a symbolic formula or a high leve l language construct (p seudo code). The follow ing symbol s are used to represe nt data mov ement, arithm etic or logi cal operators: Instruction Na me MNEM Specifies the mnemon ic opcode of the instru ction in oversiz ed bold lettering for easy refe rence. The mn emonics have been chos en with regard to the particular ope ration which is performed by the specified inst ruction. Thes e mnemonics are also u sed by tool s such as assemblers. Short D. Short description which is also used in t he comp act tables on the previo us pages.Basical ly, the following data types are possibl e: BIT, BYTE, WORD, DOUBLEWORD Except for those ins tructions w hich ex tend byte da ta to wo rd data, all inst ructions h ave only one particu lar data t ype. Not e that the data typ es mentio ned in t his subs ection do not consid er accesse s to indirec t address p ointers or to the system stack w hich are always pe rformed with wo rd data. Mo reover, no data type is sp ecified for Sys tem Control Instruct ions and for those of the branch ins tructions whic h do not access any explici tly addressed d ata. Description This part prov ides a bri ef verbal descri ption of the action tha t is exec uted by the respective instruction. http://hilalbaskul.com/images/canvassing-training-manual.pdf

Also hints are given on using the instruc tion itself, its operands, and its fla gs. Note In some c ases addi tional notes point out special circumstanc es. Condition al inst ructions refer here to the co ndition co des listed in Table 5. Condition Flags This part ref lects the state of th e N, C, V, Z and E fl ags in the PSW re gister whi ch is the state af ter execution of the correspon ding instruct ion, except if the PSW regist er itself was spec ified as th e destinati on operand of that instruc tion (see N ote).For byte operation s, the non-add ressed byte i s cleared and the addresse d byte is overwritt en. For bit or bit-fie ld operations on the PSW register, only th e specified bits are modified. Supposed th at the con dition flag s were no t selected as destinat ion bit s, they sta y unchang ed. This me ans that th ey keep th e state afte r executi on of the prev ious instru ction. In any case, if the PSW was the destin ation operand of an instru ction, the PSW flags do NOT represent t he conditio n flags of th is instruct ion as usual.M ostly, the s elected add ressing mod e combinati on is speci fied by the opcod e of the corre sponding in struction. How ever, there are so me arithmetic and logical i nstructions where th e addressi ng mode c ombination is not s pecified by the (identical) o pcodes but by particul ar bits with in the operan d field. Al l C166 Family instru ctions co nsist of 2 b ytes or 4 bytes (single wo rd or double w ord instruc tion).The table shows t he mnemon ic abbrevi ations, the test that is exec uted for a specific condition, and the inte rnal represent ation by a 4 -bit numb er.All in structions requiring multipl e cycles o r hold states t o be exe cuted are regarded a s one instruc tion in t his sense. Any instruct ion type ca n be used with the ATOMIC and EXTended i nstructions.

ATTENTION: When a ClassB trap interrup ts an ATOMIC or EXTended sequence, this sequence is termi nated, the interrupt l ock is remove d and the standard co ndition is restored, before the trap routine is executed. The remai ning instru ctions of the terminated s equence tha t are execut ed after returnin g from the trap routine will run under standard co ndition s! Wit hin a Clas sA o r Clas sB tr ap s ervi ce ro utin e EXT end i nstru ctio ns do not work (i.e. override the DPP mechani sm) as long as any of th e ClassB tra p flags is set. ATTENTION: There is only ONE counter to control the le ngth of an ATOM IC or EXTend sequence, i.e. issui ng an ATOMIC or EXTend instru ction within a seq uence will rel oad the counter w ith the value of the new instruc tion. ATOMIC and EXTend inst ructions can be nest ed to generat e longer locked se quences. When using the ATOMI C and EXTe nded instru ctions with other sys tem control o r branch instruction s, please n ote that the counter coun ts any exe cuted instru ction. Note: The ATOMIC and EXTended ins tructions are no t available in the SAB 8XC166(W) devi ces. Chap ter “ System Programmin g ” of the respecti ve User ’ s Manual des cribes the h andling of interrupted multiplic ations and divisions. Bit MDRIU is set at the s tart of a MUL ins truction (not w hen the instruc tion is resu med) or upon a w rite to regis ter MDL or MDH. Bi t MDRIU is cl eared upon a read from reg ister MDL. Bit MDR IU is affect ed by a wr ite to regist er MDC, of cou rse. When the MUL instruction is interrupte d, bit MULIP is set in the PSW o f the interrup ting routine, i.e. after pus hing the previou s PSW onto stack. This mech anism will disturb the opera nd fetching if an other instructi on (than the continue d multiplic ation) is exec uted after R ETI. For standard inte rrupt handling (ret urn to interrupted m ultiplicati on) this is done automatica lly. Task s chedulers m ust keep t rack of inte rrupted mu ltiplicatio ns in each task.

The followi ng pages of thi s sectio n contain a de tailed desc ription of each instructi on of the C166 Fa mily in al phabetical order. Cleared otherwise. Used to s ignal the end of a table. Z Set if result equals zero. Cleared otherw ise. V Set if an ar ithmetic overflo w occurred, i.e. the result cann ot be represented in the spec ified data t ype. Cleare d otherwise. C Set if a carry is generated from the mos t signific ant bit of the specif ied data type. Cleared otherwise. N Set if the mo st signific ant bit of th e result is set. Cleare d othe rwis e. Cleared otherwise. Used to s ignal the end of a table. Cleare d othe rwis e. This instruction can be us ed to perf orm multiple prec ision ar ithmetic. Cleared otherwise. Used to s ignal the end of a table. Z Set if result equals zero and the prev ious Z flag was set. Cleared o therwise. V Set if an ar ithmetic overflo w occurred, i.e. the result cann ot be represented in the spec ified data t ype. Cleare d othe rwis e. The res ult is then stored in op1. Cleared otherw ise. V Always clear ed. C Always clear ed. N Set if the mo st signific ant bit of th e result is set. Cleare d othe rwis e. The LSB is shift ed into the Carry. Only shift values betwe en 0 and 15 are allowe d. When using a GPR as the count control, only the l east signif icant 4 bits are used. Cleared otherw ise. V Set if in any cy cle of the shif t operatio n a 1 is shifted out of th e carry flag. Cle ared for a shi ft count of zero. C The carry flag is set ac cording to t he last LSB sh ifted out of op1. Clea red for a shif t count of zero. N Set if the mo st signific ant bit of th e result is set. Cleare d othe rwis e. All instruction s requiring m ultiple cy cles or hold sta tes to be ex ecuted are regarded as one instruc tion in this sense. Any i nstruction t ype can be us ed with the ATOMIC instruc tion. Note Plea se see add itional note s on Page 39. The ATOMIC instruct ion is not a vailable i n the SAB 8XC166(W) devices. Z Not affected. {-Variable.fc_1_url-

V Not affected. C Not affected. N Not affected. The result is th en stored in op1. Addressing Mn emonic Format Bytes Modes BAND bitaddr Z.z, b itaddr Q.q 6A QQ ZZ qz 4 Condition Flags EZV C N 0 NOR OR AND XOR E Always clear ed. Z Contains the logica l NOR of the two specifie d bits. V Contains the logica l OR of the two s pecified b its. C Contains the logica l AND of the tw o specified b its. N Contains the logica l XOR of th e two specifi ed bits. This instruc tion is primarily us ed for peripheral a nd system control. Addressing Mn emonic Format Bytes Modes BCLR bitadd r Q.q qE QQ 2 Condition Flags EZV C N 0B 00 B E Always clear ed. Z Contains the logica l negation of the previo us state of the speci fied bit. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s pecified bi t. No result is written by this instructio n. Only the con dition codes are updated. Note The meaning of the conditi on flags for t he BCMP inst ruction is differen t from the meanin g of the flag s for the other compare inst ructio ns. Addressing Mn emonic Format Bytes Modes BCMP bitadd r Z.z, bitaddr Q.q 2A Q Q ZZ qz 4 Condition Flags EZV C N 0 NOR OR AND XOR E Always clear ed. N Contains the logica l XOR of th e two specifi ed bits. Cle ared otherwise. V Always clear ed. C Always clear ed. N Set if the mo st significa nt bit of the word resul t is set. Cleare d othe rwis e. Cle ared otherwise. V Always clear ed. C Always clear ed. N Set if the mo st significa nt bit of the word resul t is set. Cleare d othe rwis e. The source bit is examined and the flag s are update d according ly. Addressing Mn emonic Format Bytes Modes BMOV bitadd r Z.z, bitad dr Q.q 4A QQ ZZ qz 4 Condition Flags EZV C N 0B 00 B E Always clear ed. Z Contains the logica l negation of the previo us state of the source bit. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s ource bit. Addressing Mn emonic Format Bytes Modes BMOVN bitadd r Z.z, bitad dr Q.

q 3A QQ ZZ qz 4 Condition Flags EZV C N 0B 00 B E Always clear ed. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s ource bit. The ORed res ult is then store d in op1. Addressing Mn emonic Format Bytes Modes BOR bitadd r Z.z, bitaddr Q.q 5A Q Q ZZ qz 4 Condition Flags EZV C N 0 NOR OR AND XOR E Always clear ed. N Contains the logica l XOR of th e two specifi ed bits. This ins truction is prim arily used f or peripheral a nd system control. Addressing Mn emonic Format Bytes Modes BSET bitaddr Q.q qF QQ 2 Condition Flags EZV C N 0B 00 B E Always clear ed. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s pecified bi t. The XORed resu lt is then s tored in op1. Addressing Mn emonic Format Bytes Modes BXOR bitaddr Z.z, b itaddr Q.q 7A QQ ZZ qz 4 Condition Flags EZV C N 0 NOR OR AND XOR E Always clear ed. N Contains the logica l XOR of th e two specifi ed bits. The value o f the instruc tion pointe r, IP, is place d onto the s ystem stack. Beca use the IP al ways point s to the instruct ion followi ng the branch ins truction, the value s tored on the system sta ck represents th e return address of the calling rout ine. If the c ondition is not met, no acti on is taken and the ne xt instructio n is executed normally. Note The condition codes for op 1 are defined in Table 5. Addressing Mn emonic Format Bytes Modes CALLA cc, caddr CA c0 M M MM 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Because th e IP always points to th e instructio n followi ng the branch ins truction, the value s tored on the system sta ck represents th e return address of the calling rout ine. Z Not affected. V Not affected. C Not affected. N Not affected. The v alue of the instruct ion pointer (IP) is plac ed onto the system s tack.

Beca use the IP always poin ts to the ins truction following the branch instruction, the value stored on the sys tem stack represents th e return addres s of the ca lling routine. The value o f the IP used in the targe t address ca lculation is the add ress of t he instructi on followi ng the CA LLR inst ruction. Addressing Mn emonic Format Bytes Modes CALLR rel BB rr 2 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. The value of the instruc tion pointer (IP) is plac ed onto the system s tack. Beca use the IP always poin ts to the ins truction following the branch instruction, the value stored on the sys tem stack represents th e return addres s to the ca lling routine. The previous va lue of t he CSP is also p laced on the system s tack to ins ure correct return to the calling segment. Addressing Mn emonic Format Bytes Modes CALLS seg, caddr DA SS MM MM 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. The f lags are se t according to the rules of su btraction. The operand s remain unchan ged. Cleared otherw ise. V Set if an arit hmetic u nderflow occu rred, i.e. the re sult canno t be represente d in the specified da ta type. Clea red otherwise. C Set if a borrow is generat ed. Cleare d othe rwis e. The f lags are se t according to the rules of su btraction. Cleare d othe rwis e. The so urce operand sp ecified by op1 is compa red to the source opera nd specifie d by op2 by perfo rming a 2 ’ s compl ement binary sub traction of op2 from op 1. Operand op1 may sp ecify ONLY GPR regi sters. O nce the subtrac tion has c ompleted, th e operand op1 is decremented by one. Using the set flags, a b ranch instruction can then b e used in c onjunction with this ins truction to form common high leve l language FOR loops of any range. O nce the subtrac tion has c ompleted, th e operand op1 is decremented by two. Using the s et flags, a branc h instruction can then b e used in c onjunction with this ins truction to form common high leve l language FOR loops of any range. Cleare d othe rwis e. O nce the subtrac tion has c ompleted, th e operand o p1 is i ncremented by one. Using the set flags, a branch instruction can then b e used in c onjunction with this ins truction to form common high leve l language FOR loops of any range. Cleare d othe rwis e. O nce the subtrac tion has c ompleted, th e operand o p1 is i ncremented by two. Using th e set flags, a branch instruction can then b e used in c onjunction with this ins truction to form common high leve l language FOR loops of any range. Cleare d othe rwis e. The watchdog tim er is enable d by a reset. The DISWDT i nstruction allow s the watchdog timer to be dis abled f or applications which do no t require a watchd og function. Following a reset, this in struction ca n be executed at any time until either a Service Watc hdog Timer instruction (SRVWDT) or an End of Initialization in struction (EINIT) are execute d. Once one of these inst ructions has been execu ted, the DISWDT instruction will have no effect. Note To i nsure that th is instructi on is not a ccidentall y executed, it is implement ed as a prote cted instruc tion. Addressing Mn emonic Format Bytes Modes DISWDT A5 5A A5 A5 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Note DIV is interruptable. Please see additional description on Page 40. Cleared otherw ise. V Set if an arit hmetic ove rflow occurre d, i.e. if the divisor (op1) was zero (the result in MDH and MDL is not valid in this case). Cleared o therwise. C Always clear ed. N Set if the mo st signific ant bit of th e result is set. Cleare d othe rwis e. Note DIVL is interruptabl e. Please see additional description on Page 40. Cleared otherw ise. V Set if an arithmetic over flow occurred, i.e. the quotien t cannot be represente d in a word data type, or if the di visor (op1) wa s zero (the res ult in MDH an d MDL is not v alid in thi s case). Cleare d othe rwis e. Note DIVLU is interruptable. Cleare d othe rwis e. Note DIVU is interru ptable. Cleare d othe rwis e. Aft er a reset, the re set output pi n RSTOUT is pul led low. It remains low until the EINIT instruction has been executed at which tim e it goes h igh. This en ables the p rogram to sig nal the external ci rcuitry that i t has s uccessful ly initiali zed the microcontro ller. After the EIN IT instructi on has been executed, execution of the Dis able Watchd og Timer inst ruction (DISWDT) has no effe ct. Addressing Mn emonic Format Bytes Modes EINIT B5 4A B5 B5 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Note Plea se see add itional note s on Page 39. The EXTR instructi on is not a vailable i n the SAB 8XC166(W) devices. Z Not affected. V Not affected. C Not affected. N Not affected. The val ue of op2 define s the length of the e ffected ins truction seq uence. The EXTP instruc tion is not available in th e SAB 8XC166(W) devices. Condition Flags EZV C N ----- E Not affected. The EXTPR inst ruction is not a vailable in the SAB 8XC166(W) devices. The value o f op2 de fines the l ength of the effected ins truction seque nce. The EXTS instruc tion is not available in th e SAB 8XC166(W) devices. Z Not affected. V Not affected. C Not affected. N Not affected. The long or in direct addres s itself rep resents the 1 6-bit segment of fset (address bits A15 - A0). The value o f op2 de fines the l ength of the effected ins truction seque nce. The EXTSR inst ruction is not a vailable in the SAB 8XC166(W) devices. In both modes the CPU is powered dow n. In idle mode the perip herals remain runn ing, while in sleep mo de also t he peripherals are po wered dow n. The device remains po wered dow n until a p eripheral inte rrupt (only po ssible in Idle mode) o r an external interrupt occ urs. Sleep mode must be sel ected before executing the IDLE inst ructio n. Note To i nsure that th is instructi on is not a ccidentall y executed, it is implement ed as a prote cted instruc tion. Addressing Mn emonic Format Bytes Modes IDLE 87 78 87 87 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. The value of the IP used in the ta rget address calculati on is the address of the inst ruction f ollowing the JB instruc tion. If the specified bit is clear, the in struction fol lowing the JB i nstruction i s execut ed. Addressing Mn emonic Format Bytes Modes JB bitadd r Q.q, rel 8A QQ rr q0 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Th e displace ment is a two ’ s comple ment number whi ch is sign extended an d counts the relative di stance in word s. The value of the IP use d in the targ et address ca lculation is the a ddress of th e instructio n followin g the JBC instru ction. If the specified bit was clear, the inst ruction following the JBC instruc tion is ex ecuted. Addressing Mn emonic Format Bytes Modes JBC bitadd r Q.q, rel AA QQ rr q0 4 Condition Flags EZV C N 0B 00 B E Always clear ed. Z Contains logical negation of t he previou s state of the s pecified bit. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s pecified bi t. Note The condition codes for op 1 are defined in Table 5. Addressing Mn emonic Format Bytes Modes JMPA cc, caddr EA c0 M M MM 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Note The condition codes for op 1 are defined in Table 5. Z Not affected. V Not affected. C Not affected. N Not affected. If the speci fied condi tion is not m et, program execution continues normally w ith the ins truction foll owing the JMPR inst ruction. Addressing Mn emonic Format Bytes Modes JMPR cc, rel cD rr 2 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. The value of the IP used in the ta rget address calculati on is the address of the inst ruction f ollowing the JNB ins truction. If th e specified bit is set, the ins truction foll owing the JNB ins truction is execut ed. Addressing Mn emonic Format Bytes Modes JNB bitadd r Q.q, rel 9A QQ rr q0 4 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Th e displace ment is a two ’ s comple ment number whi ch is sign extended an d counts the relative di stance in word s. The value of the IP use d in the targ et address ca lculation is the a ddress of th e instructio n followin g the JNBS instruc tion. If the specified bit was set, th e instructio n following the JNBS instruc tion is ex ecuted. Addressing Mn emonic Format Bytes Modes JNBS bitadd r Q.q, rel BA QQ rr q0 4 Condition Flags EZV C N 0B 00 B E Always clear ed. V Always clear ed. C Always clear ed. N Contains the previous s tate of the s pecified bi t. Cleared otherwise. Used to s ignal the end of a table. Z Set if the va lue of the s ource operan d op2 equal s zero. Cleared o therwise. V Not affected. C Not affected. N Set if the mos t significan t bit of the so urce operand o p2 is set. Cleared o therwise. Cleared otherwise. Used to s ignal the end of a table. Cleared o therwise. Z Set if the va lue of the s ource operan d op2 equal s zero. Cleared o therwise. The co ntents of the moved data is ex amined, and the condition codes are u pdated a ccordingly. Cleared o therwise. V Not affected. C Not affected. N Always clear ed. Note MUL i s interruptabl e. Please see additional description on Page 40. Z Set if the res ult equals zero. Cleared ot herwise. V This bit is set if the re sult canno t be represent ed in a wo rd data type. Cleared oth erwise. C Always clear ed. N Set if the mo st signific ant bit of th e result is set. Cleare d othe rwis e. Note MULU is interrupt able. Cleare d othe rwis e. The result is th en stored in op1. Cleare d othe rwis e. A null operation c auses no c hange in th e status of the flag s. Addressing Mn emonic Format Bytes Modes NOP CC 00 2 Condition Flags EZV C N ----- E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. The res ult is then stored in op1. Cleare d othe rwis e. Because IP a lways points to the i nstruction fo llowing t he branch inst ruct ion, t he val ue s tored on th e syst em sta ck re pres ents the return ad dress of the calling rout ine. Cleare d otherwise. Used t o signal the end of a table. Z Set if the va lue of t he pushed opera nd op1 equa ls zero. Cleared o therwise. V Not affected. C Not affected. N Set if the most sig nificant bit of the pushed opera nd op1 is set. Cleared o therwise. Cleared o therwise. Use d to signal the end of a table. Z Set if the va lue of the p opped word equals zero. Cleared othe rwis e. V Not affected. C Not affected. N Set if the mo st signific ant bit of th e popped word i s set. Cleared o therwise. Z Set if the sou rce operan d op2 equals zero. Cleared oth erwise. V Always clear ed. C Always clear ed. N Always clear ed. Cleared o therwise. Use d to signal the end of a table. Z Set if the va lue of the p ushed word equals ze ro. Cleared othe rwis e. V Not affected. C Not affected. N Set if the mo st signific ant bit of th e pushed word is set. Cleared o therwise. In this mode, all periph erals and the CPU a re powered down unt il the part is externally reset.